Moore's law predicts that the number of transistors that can be placed on an integrated circuit (IC) is doubled approximately every two years. However, as the number of transistors increases and their size decreases, smaller physical gate end to end spacing is required. It has been found, though, that smaller physical gate end to end spacing is becoming ever more difficult to achieve. This, in turn, will limit the density and performance achieved by further scaling of devices.
By way of example, at a 32 nm node, it is currently possible to only achieve an approximate 75 nm end to end spacing between adjacent gate structures, i.e., replacement gate structures or hybrid replacement gate structures. Accordingly, physical gate end to end spacing is not scaling well, particularly with the need for multiple exposures and processes to form the gate structures. In fact, replacement gate processes, e.g., exposure, etching and deposition processes, may even contribute to shorting of the gate structures (i.e., end to end touching of the gate material). Accordingly, end to end spacing, going forward, may even degrade device performance.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.